A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI

Multiproject chip implementation has been used in teaching analog MOS circuit design. After having worked with computer simulation and layout aids in homework problems, students designed novel circuits including several high performance op amps, an A/D converter, a switched capacitor filter, a 1 K dynamic RAM, and a variety of less conventional MOS circuits such as a VII converter, an AC/DC converter, an AM radio receiver, a digitally-controlled analog signal processor, and on-chip circuitry for measuring transistor capacitances. These circuits were laid out as part of an NMOS multiproject chip. Several of the designs exhibit a considerable degree of innovation; fabrication pending, computer simulation shows that some may be pushing the state of the art. Several designs are of interest to digital designers; in fact, the course has provided knowledge and technique needed for detailed digital circuit design at the gate level

Compact Models and the Physics of Nanoscale FETs

The device physics of nanoscale MOSFETs is reviewed and related to traditional compact models. Beginning with the Virtual Source model, a model for nanoscale MOSFETs expressed in traditional form, we show how a Landauer approach gives a clear, physical interpretation to the parameters in the model. The analysis shows that transport in the channel is limited by diffusion near the virtual source both below and above threshold, that current saturation is determined by velocity saturation near the source, not by the maximum velocity in the channel, and that the channel resistance approaches a finite value as the channel length approaches zero. These results help explain why traditional models continue to work well at the nanoscale, even though carrier transport is distinctly different from that at the microscale, and they identify the essential physics that physics-based compact models for nanoscale MOSFETs should comprehend

SiGe-On-Insulator (SGOI) Technology and MOSFET Fabrication

In this work, we have developed two different fabrication processes for relaxed Si₁₋xGex-on-insulator (SGOI) substrates: (1) SGOI fabrication by etch-back approach, and (2) by "smart-cut" approach utilizing hydrogen implantation. Etch-back approach produces SGOI substrate with less defects in SiGe film, but the SiGe film uniformity is inferior. "Smart-cut" approach has better control on the SiGe film thickness and uniformity, and is applicable to wider Ge content range of the SiGe film. We have also fabricated strained-Si n-MOSFET’s on SGOI substrates, in which epitaxial regrowth was used to produce the surface strained Si layer on relaxed SGOI substrate, followed by large-area n-MOSFET’s fabrication on this structure. The measured electron mobility shows significant enhancement (1.7 times) over both the universal mobility and that of co-processed bulk-Si MOSFET’s. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si₁₋xGex layer.Singapore-MIT Alliance (SMA

MOSFET Channel Engineering using Strained Si, SiGe, and Ge Channels

Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in strained Si and dual channel heterostructures, and also introduce high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and electron transport in these devices, we have fabricated nearly symmetric mobility p- and n-MOSFETs on a common Si₀.₅Ge₀.₅ virtual substrate.Singapore-MIT Alliance (SMA

Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on SiââxGex/Si virtual substrates

We have fabricated strained Ge channel p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Siâ.âGeâ.â virtual substrates. The poor interface between silicon dioxide (SiOâ) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400° C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly 8 times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm²/V-s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement mode MOSFET with buried channel-like transport characteristics.Singapore-MIT Alliance (SMA

Statistical Modeling with the Virtual Source MOSFET Model

A statistical extension of the ultra-compact Virtual Source (VS) MOSFET model is developed here for the first time. The characterization uses a statistical extraction technique based on the backward propagation of variance (BPV) with variability parameters derived directly from the nominal VS model. The resulting statistical VS model is extensively validated using Monte Carlo simulations, and the statistical distributions of several figures of merit for logic and memory cells are compared with those of a BSIM model from a 40-nm CMOS industrial design kit. The comparisons show almost identical distributions with distinct run time advantages for the statistical VS model. Additional simulations show that the statistical VS model accurately captures non-Gaussian features that are important for low-power designs.Masdar Institute of Science and Technolog

III-V CMOS: What have we learned from HEMTs?

The ability of Si CMOS to continue to scale down transistor size while delivering enhanced logic performance has recently come into question. An end to Moore's Law threatens to bring to a halt the microelectronics revolution: a historical 50 year run of exponential progress in the power of electronics that has profoundly transformed human society. The outstanding transport properties of certain III-V compound semiconductors make these materials attractive to address this problem. This paper outlines the case for III-V CMOS, harvests lessons from recent research on III-V High Electron Mobility Transistors (HEMTs) and summarizes some of the key challenges in front of a future III-V logic technology

Engineering the Electron-Hole Bilayer Tunneling Field-Effect Transistor

The electron-hole (EH) bilayer tunneling field-effect transistor promises to eliminate heavy-doping band tails enabling a smaller subthreshold swing voltage. Nevertheless, the electrostatics of a thin structure must be optimized for gate efficiency. We analyze the tradeoff between gate efficiency versus ON-state conductance to find the optimal device design. Once the EH bilayer is optimized for a given ON-state conductance, Si, Ge, and InAs all have similar gate efficiency, around 40%-50%. Unlike Si and Ge, only the InAs case allows a manageable work function difference for EH bilayer transistor operation.National Science Foundation (U.S.). Center for Energy Efficient Electronics Science (Award 0939514

Si Industry at a Crossroads: New Materials or New Factories?

Many trends in the silicon industry could be interpreted as the herald of the end of traditional Si scaling. If this premise holds, future performance and system-on-chip applications may not be reached with conventional Si technology extensions. We review progress towards our vision that a larger crystal structure on Si, namely relaxed SiGe epitaxial layers, can support many generations of higher performance Si CMOS and new system-on-chip functionality without the expense of significant new equipment and change to CMOS manufacturing ideology. We will review the impact of tensile strained Si layers grown on relaxed SiGe layers. Both NMOS and PMOS exhibit higher carrier mobilities due to the strained Si MOSFET channel. Heterostructure MOSFETs designed on relaxed SiGe can have multiple-generation performance increases, and therefore determine a new performance roadmap for Si CMOS technology, independent of MOSFET gate length. We also indicate that this materials platform naturally leads to incorporating new optical functionality into Si CMOS technology.Singapore-MIT Alliance (SMA